Depending on the PFL design, 100MHz is likely to fail timing for C5 devices.

For example, when selecting Flash Programming and FPGA Configuration, setting the input frequency to 100MHz, and compiling in FPP mode, the maximum operating frequency was about 80MHz to 95MHz.

Therefore, we recommend that you create a PFL sample design, check the compilation results, and determine the speed grade of your device.
Please note that an accurate timing report will not be generated if timing constraints are not included.

Reference information
Quartus® Getting Started Guide - Timing Constraint Methods