Intel: When using the JTAG Constraint in the Timing Analyzer Cookbook to set the FPGA configuration from the JTAG 10pin header, the TDO will result in a Timing Error if the TCK of the Intel® FPGA Download Cable II is set to the default 24MHz

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Intel: When using the JTAG Constraint from the Timing Analyzer Cookbook with the JTAG 10pin Header to FPGA configuration setting, the TDO of the Intel® FPGA Download Cable II has a Timing Error when the TCK is set to 24MHz, which is Default.

Quartus Prime Timing Constraints/Analysis

Category: Timing Constraint/Analysis
Tools: Quartus® Prime
Device:-

[Timing Analyzer Cookbook]
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf#page=18

I need to reduce the frequency of the Intel® FPGA Download Cable II (formerly USB-Blaster™ II) to converge timing errors.
The parameters of the Intel® FPGA Download Cable II are 24/16/6MHz, and can be changed as follows.

[parameter]
ub2_default_t_period: 41.666ns
ub2_safe_t_period: 62.5ns
ub1_t_period: 166.666ns

<Change example>
[Default]
set tck_t_period $ub2_default_t_period

[Change to 6MHz]
set tck_t_period $ub1_t_period

Please refer to the following article for changing the TCK frequency of the actual cable.
[Let's change the TCK frequency of USB-Blaster™ II]
https://www.macnica.co.jp/business/semiconductor/articles/intel/130581/

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