Intel: I would like to configure the Clock/Data skew adjustment register provided in the Ethernet PHY device from the HPS (Ethernet MAC controller) of the Cyclone® V SoC / Arria® V SoC. How should I set the PHY registers?

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Intel: I would like to set the Clock/Data skew adjustment registers provided in the Ethernet PHY device from the Cyclone® V SoC / Arria® V SoC's HPS (Ethernet MAC Controller). How should I set the PHY registers?

SoC FPGAs

Category: SoCs
tool:-
Device: Arria® V, Cyclone® V

There is no mechanism or register for skew adjustment on the HPS side, so it is necessary to set up the registers on the PHY side according to the specifications of the PHY device.

The PHY device register setting interface is either an MDIO connection or an I2C connection.

The Ethernet Controller has two choices for the management control interface used for configuration and status monitoring of the PHY:

Management Data Input/Output (MDIO)
I2C PHY management through a separate I2C module within the HPS

For information on how to control MDIO, refer to the information at the link below.
https://www.macnica.co.jp/business/semiconductor/support/faqs/intel/120865/

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