Category: SoCs
tool:-
Device: Cyclone® V


MDIO is controlled by the following two registers.
・Register 4 (GMII Address Register)
・Register 5 (GMII Data Register)

Triggers are given by the gb bit (bit0) of Register 4.

When reading, the gb bit is set to 1:Busy to start MDIO transmission and reception, and when completed, the gb bit is cleared to 0:Not Busy.
(See Register 5 data later.)

When writing, set Register 4 (gb=1:Busy) after setting the data to be written to Register 5.
By setting the gb bit to 1:Busy in the same way as when reading, MDIO transmission/reception is started, and when completed, the gb bit is cleared to 0:Not Busy.

As information that can be used as a reference, you can refer to u-boot and linux driver processing.
Register 4/5 are controlled by the following files/functions, respectively.

u-boot
File: drivers/net/designware.c
Functions: eth_mdio_read, eth_mdio_write

linux
File: drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
Functions: stmmac_mdio_read, stmmac_mdio_write