Category: Tool
Tools: Quartus® Prime Standard Edition, Quartus® Prime Lite Edition
Device: MAX® 10

The MAX 10 E144 package has PLL Clock Input Pins guidelines.
It is recommended not to assign output pins to the left or right of the PLL clock input pin.

■ 3.10. Guidelines: Clock and Data Input Signal for Intel MAX 10 E144 Package
[PLL Clock Input Pins]
The PLL clock input pins are sensitive to SSN jitter. To avoid the PLL from losing lock, do not use the output pins directly on the left and right of the PLL clock input pins.

However, assigning an output pin to the right or left of the PLL clock input pin may not result in a compilation error.
Error(18496) The Output <name> in pin location <name> (pad_<number>) is too close to PLL clock input pin (<name>) in pin location <name> (pad_<number>)

In that case as well, Altera® recommends following the PLL Clock Input Pins guidelines.

<Related FAQ>
On a MAX 10 device, assigning a user I/O pin next to the PLL input clock results in the following error and the placement fails.