<Message>
Error (18496): The Output in pin location (pad_) is too close to PLL clock input pin () in pin location (pad_)

Category: Specifications
Tools: Quartus® Prime / Quartus II
Device: MAX® 10

This error only occurs in the E144 package of MAX 10 devices.
The PLL clock input pin is sensitive to Simultaneous Switching Noise (SSN) jitter.
For MAX 10 devices in the E144 package, output and bidirectional pins cannot be placed to the left or right of the PLL clock input pin to ensure stable operation of the PLL.

For details, please refer to the following document.
https://docs.altera.com/r/docs/683572/current/max-10-fpga-signal-integrity-design-guidelines/guidelines-clock-and-data-input-signal-for-max-10-e144-package
(Refer to PLL Clock Input Pins in the Clock and Data Input Signal for MAX 10 E144 Package section.)

<Caution>
Please note that in versions prior to Quartus Prime v16.0, placing output or bidirectional pins to the left or right of the PLL input clock does not result in the above error (ID:18496).