Event concluded: Thursday, April 23, 2026, 13:30-14:30

How to use the new Questa Advanced Simulator Visualizer debug environment

Visualizer is a new GUI debug window for Questa Advanced Simulator. Compared to the existing GUI, it offers improved performance for debugging simulations, and has enhanced waveform display, simulation result analysis, and debugging functions. It offers a range of features that Questa Advanced Simulator users should definitely take advantage of. In this seminar, we will introduce basic simulation methods and various debugging functions using Visualizer.

On-demand! (Always available to watch)

How to distinguish between asynchronous clock domains that are often overlooked - FPGA Edition

As FPGA operating frequencies improve and the number of clock domains and registers increases, metastability occurs due to clock domain crossing (CDC) data transfer between asynchronous clocks within the circuit, and this leads to an increasing number of malfunctions.
This seminar will explain the problem of metastability and how to verify it using Questa CDC.

*Renewed and made available on demand (from January 28, 2026)

Applications are now being accepted: Thursday, June 4, 2026, 13:30-14:30

Improving RTL quality early on

Questa Lint performs syntax, semantic, stylistic, and structural analysis early in the design process, improving design quality, development predictability, and easing pressure on project schedules by detecting problems early that would be costly to fix later.
In this seminar, we will introduce the overview and features of Questa Lint with demonstrations.

On-demand! (Always available to watch)

Increase efficiency with HDL Designer! Improve FPGA design quality and utilize design assets

HDL Designer is a development support tool packed with useful features for RTL designers. It not only shortens the time required to create RTL and specifications, but also improves design visibility, making it ideal for block reuse and team design. In this seminar, we will introduce how to use the tool to improve HDL design quality, increase overall design quality, and reduce development time by efficiently reusing design assets (existing designs).

*Renewed and made available on demand (from January 28, 2026)

Applications are now being accepted: Thursday, June 18, 2026, 13:30-14:30

Eliminate risks and overcome challenges in the FPGA design process

Logic synthesis and placement and routing optimization technologies, which are constantly evolving, are performed using complex algorithms, but if there is a flaw in this optimization, problems will occur in the netlist, causing malfunctions in the actual device. To resolve defects and issues that arise from implementation, equivalence checking, which is used in ASIC development, is used. Even for FPGAs, equivalence checking between RTL and netlist is recommended by major functional safety standards.
In this seminar, we will introduce how equivalence verification technology for FPGAs can overcome the risks and challenges of introducing defects during implementation, as well as the necessary verification methods and customer examples.

Applications are now being accepted: Tuesday, June 16, 2026, 13:30-14:30

Circuit and board design for cost, quality and speed

Developing efficient electronic boards that take into account cost, quality, and speed requires a balanced range of knowledge, but if efficiency can be achieved, it should also be possible to reduce the burden on designers.
In this day and age when the wave of labor shortage is sweeping over electrical design, it is essential to improve the efficiency of electrical design.This seminar will provide a wide range of explanations based on the latest trends in electronic board development.

Event concluded: Tuesday, April 7, 2026, 13:30-14:30

Rediscover the basics of signal integrity analysis and the effectiveness of pre-analysis

In this online seminar, we will first explain the basics of SI analysis, such as the IBIS model, which is essential for analysis, what SI analysis is, and how to interpret the analysis results.
We will also explain how to use pre-analysis to balance cost and quality, and how to use SI analysis tools to optimize the design.

Applications are now being accepted: Tuesday, May 19, 2026, 13:30-14:30

Gain a deeper understanding of SerDes design evaluation and analysis

Learn about the basics of board design when using SERDES circuits, and explain the benefits of circuit designers being involved in the quality of boards including SERDES.

With the latest analysis methods, functions have been released that allow circuit designers to easily use analysis. In this seminar, we will put ourselves in the shoes of a circuit designer and provide early-stage countermeasures, including explanations of the simple operation of analysis tools.

Event concluded: Tuesday, April 14, 2026, 13:30-14:30

Benefits and Effects of Introducing Analysis Tools to Power Distribution Network Design

If "appropriate PDN design" is not achieved, there is a possibility that excessive measures have been taken in manufacturing the board.
This webinar will review the basics of PDN design and explain what electrical designers need to be aware of when designing a PDN.

Applications are now being accepted: Tuesday, May 26, 2026, 13:30-14:30

DDR4 PDN Impedance and Correlation Between Analysis and Measurement

In order to create high-quality electronic boards, quality confirmation through PDN (Power Delivery Network) analysis plays a very important role. In this webinar, we will introduce best practices for PDN analysis for DDR4, and use the HyperLynx PDN Decoupling Optimizer to suggest appropriate capacitor types and locations to determine the final capacitors and confirm how much reduction can be achieved.

Applications are now being accepted: Wednesday, May 12, 2026, 13:30-15:00

FPGA board design methodology aiming for zero revisions

We will explain the board design know-how for designing boards without revisions, based on guidelines for board design using FPGAs and recent examples of problems.

<Part 1> We will explain the basic board design guidelines that you should know when designing boards using FPGAs, as well as new verification points that have emerged from our technical support experience, using actual examples of problems.
<Part 2> Introducing HyperLynx DRC, a tool that can automatically check the checkpoints from Part 1 using PCB data

Applications are now being accepted: Tuesday, June 2, 2026, 13:30-14:30

Shortening the time required for checking circuit board drawings and reducing the burden on engineers

For designers who need help with PCB inspection, we will guide you through the basics of checking the quality of your PCB design.
We also identify problems with traditional visual inspection and propose inspection methods that are less burdensome for designers.

End date: Wednesday, March 4, 2026, 13:30-16:30 (deadline: March 2) / Venue: Siemens EDA Japan Tokyo Headquarters (Shinagawa)

[Real-Life Workshop] Utilizing the HyperLynx Series: Efficient Design Verification and Signoff across the PCB Design Flow

There are many challenges in PCB design, such as ensuring quality and design efficiency.
In particular, in the field of verification, there are many cases where defects are discovered during retroactive verification or actual device evaluation, resulting in significant losses due to rework. To address these issues, we will introduce a verification solution using the HyperLynx series that allows you to experience verification methods in real time and aims to reduce rework through shift-left approach.