UVLO (low voltage malfunction prevention function)

It provides UVLO protection for VDD on the primary side and both gate driver outputs to VCCA and VCCB on the secondary side.

​UVLO is 2.8Vtyp for primary side supply voltage 3~5V. Regarding the UVLO of the supply voltage for the gate driver output side of VCCA and VCCB on the secondary side, each voltage can be optionally selected as shown in Table 3 below.

The optimum gate drive voltage value differs between driving a silicon MOSFET and driving a SiC MOSFET​. You can select.

​Fig.54 below shows the timing chart for UVLO protection.

ENABLE or DISABLE mode

Fig. 49 shows the response time depending on ENABLE or DISABLE mode of operation.

As shown in the ENABLE version of Fig. 49(a), when the ENA/DIS(ENABLE) pin voltage goes to a LOW state, both outputs (OUTA&OUTB) are shut down simultaneously and the ENA/DIS(ENABLE) pin goes HIGH (or left open), it works fine in ENABLE mode.

Conversely, when the ENA/DIS(DISABLE)​ ​pin voltage goes to a HIGH state, both outputs (OUTA&OUTB) are shut down simultaneously and the ENA/DIS(DISABLE)​ ​pin is When pulled LOW (or left open), it works normally in DISABLE mode.

Dual input and single input

This product can set the input signal configuration with the ANB terminal.

As shown in the table below (Table.2), you can select the configuration from input channel to output channel (e.g. single input - dual output or dual input - dual output) and shutdown function (e.g. ENABLE or DISABLE). , which has four modes of operation.

The figure below shows an example of ANB pin connection, and Fig.53 shows a timing chart of input/output and shutdown function by ANB pin and ENA/DIS pin.

programmable dead time

If the dead time between two external input signals (between the INA signal and the INB signal) is shorter than the internally set dead time (DT1 and DT2), the dead time is automatically inserted. Otherwise, if the dead time of the external input signal is greater than the internal dead time, the dead time is unchanged by the gate driver and internal dead time definitions, as shown in Fig.50.

Deadtime monitors input timing and prevents output cross-conduction (such as a problem in a half-bridge configuration where both outputs are on at the same time).

In dead time control, 3 There are two modes.

・ mode A: pin 6 (DT) floating.
20ns or less [Minimum dead time tDTMIN(typ)=10ns] dead time of , thus inhibiting cross-conduction of both channel outputs.

・ mode B: pin 6 (DT) the external resistor (1 kΩ ~ 300 kΩ) to adjust the dead time
tDT (in ns) = 10 x RDT (in kΩ)

・ mode C: pin 6 (DT) of VDD connect to
Cross-conduction protection for both channel outputs is disabled. (Non-half-bridge applications).

The figure below Fig.58 shows the timing chart of dead time control mode.

negative bias

When driving SiC MOSFETs, careful consideration is required to take full advantage of the operating characteristics of SiC. The gate driver must be able to supply +20 V​ ​and a negative bias of-2V to -5V. Parasitic inductance due to non-ideal PCB layout or long package leads can cause ringing in the power transistor's gate-source drive voltage during high di/dt and dv/dt switching.

There is even a risk of unintentional turn-on or shoot-through if the ringing exceeds the threshold voltage. Applying a negative bias to the gate drive is a common way to keep such ringing below threshold. A negative voltage can improve the noise immunity of SiC MOSFETs and suppress unintended turns. Figures 63 and 64 show examples of implementing a negative gate drive bias.

CMTI (Common Mode Transient Immunity)

The figure below shows the characteristics of CMTI.

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