MAX 10 FPGA Overview - Intel -Macnica

Altera's MAX ^® 10 FPGA revolutionizes non-volatile FPGA integration by delivering advanced processing power in a low-cost, single-chip, small-form-factor programmable logic device. Inheriting the single-chip configuration of the previous MAX device family, it uses a single or dual core power supply to achieve densities from 2K to 50K LEs. The MAX 10 FPGA family offers advanced small wafer scale packages (3 mm x 3 mm) as well as high I/O pin count packages.

MAX 10 FPGAs are manufactured with TSMC's 55nm embedded NOR flash technology to enable instant-on functionality. Features such as an analog-to-digital converter (ADC) and dual configuration flash memory that can store two images and switch dynamically are included on a single chip. Unlike CPLDs, MAX 10 FPGAs have full-featured FPGA features such as Nios ^® II soft core embedded processor support, digital signal processing (DSP) blocks, and soft DDR3 memory controllers.

Take a virtual tour inside the Altera MAX 10 FPGA and see the benefits of dual configuration and true fail-safe upgrades enabled by on-die flash memory. (1:32)

MAX 10 FPGAs deliver system-level cost savings through higher integration of system component functions.

Dual configuration flash memory

Supports dual configurations with a single on-die flash memory and can be reprogrammed thousands of times for true fail-safe upgradeability

analog block

Analog block with integrated ADC and temperature sensor helps reduce latency, save board space, and allows for more flexible sampling sequences

instant on

As the first device available on the system board, the MAX 10 FPGA can also control the startup of other components such as high-density FPGAs, ASICs, ASSPs, and processors

Nios® II soft core embedded processor

MAX 10 FPGAs support integration of Altera's soft-core Nios II embedded processor, offering embedded system developers a fully configurable, instant-on, single-chip processor subsystem

DSP block

As a non-volatile FPGA with DSP, MAX 10 FPGAs are ideal for high-performance, precision applications with built-in 18x18 multipliers

DDR3 external memory interface

MAX 10 FPGAs support DDR3 SDRAM and LPDDR2 interfaces with soft IP memory controllers, ideal for video, datapath, and embedded applications

user flash

Code storage to up to 736 KB of on-die user flash memory for advanced single-chip Nios II embedded applications. Amount of user flash available is determined by configuration options

To learn more about what MAX 10 FPGAs have to offer, please see below.

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Introducing the MAX® 10 Nios® II Embedded Evaluation Kit (NEEK) Development Kit

MAX 10 NEEK

Terasic's MAX® 10 Nios® II Embedded Evaluation Kit (NEEK) is a full-featured embedded evaluation kit based on the MAX 10 FPGA family. It is a comprehensive design environment that provides embedded system developers with everything they need to develop processor-based systems, including hardware, development tools, IP (Intellectual Property), and an integrated platform including reference designs.