Functions implemented in hardware

Configuration memory

The FPGA loses its configuration image when the power is turned off. The MAX 10 FPGA automatically transfers the configuration image stored in the flash memory to the FPGA every time the power is turned on.

• Built-in flash memory for configuration eliminates the need for an external configuration memory.
• When the power is turned on, it starts working within a few milliseconds (instant-on).
• The configuration image is not lost when power is removed (non-volatile).
• Since the flash process is used, reprogramming (erase and write) to the flash memory can be performed up to 10,000 times.
• ​The area that can be used by the user for purposes other than configuration (UFM (User Flash Memory))) is up to 736Kb.
• Stores two configuration images (dual configuration) and you can switch them dynamically (on the fly).

<Usage examples that make the most of the features>

LE (logic element)

• A MAX 10 FPGA has up to 50,000 LEs. Since the maximum number of LEs of MAX V CPLD is 2,210, it is about 23 times larger.

LE is a part of FPGA to make logic circuit. If you use this, you can also make a processor, so you can make a high-performance microcomputer.

analog block

• It has a 12-bit, 1Msps (million samples per second) ADC (Analog-to-Digital Converter) with up to 18-channel input and a TSD (Temperature Sensing Diode) for correction.

Analog signals from voice and various sensors can be converted to digital signals by ADC and then processed digitally.

internal memory

• It has up to 1.6Mb of SRAM.
• As mentioned in the configuration memory section, UFM is also available up to 736Kb.

DSP (Digital Signal Processor) block

• Equipped with a DSP that can configure up to 144 18x18 multipliers and up to 288 9x9 multipliers.

Multipliers can also be made with LEs, but a single 18x18 multiplier uses hundreds of LEs. Therefore, if you use the optimized parts "DSP" to make a multiplier, you can make a multiplier faster than LE without using LE.

oscillator

• It has an internal oscillator that generates a clock signal.
  It works just by turning on the power, so it can be used for watchdog timers and sleep controllers.

global clock line

• It has up to 20 global clock lines.
  A global clock line is a low-delay and low-skew routing that connects directly to each cell, such as an LE or DSP.
  Use for clocks and reset signals with high fanout (connected to many cells such as LEs).

PLL (Phase Locked Loop)

• Equipped with up to four PLLs that divide/multiply the clock signal and match the phase.

The PLL can generate 10 stable internal clocks with different frequencies and 2 external clock signals from a single clock signal.

AES (Advanced Encryption Standard)

• Since the flash memory and FPGA are mounted on a single chip, the product is structurally stronger in security than placing the flash memory externally. AES.

I/O

• Supports 3.3V, LVDS, mini-LVDS, PCI and over 30 I/Os as standard.

EMIF (external memory interface)

• You can use the controller provided with the IP to interface with externally located memory such as SRAM, DDR2/3 and LPDDR2.

voltage regulator

• There are products that supply dual power supplies of 2.5V and 1.2V and single supply products of 3.3V (or 3V).

Single-supply products have integrated regulators that generate the 2.5V and 1.2V supplies required by the FPGA core, reducing the number of external power devices required. Dual power products require two power supplies but offer better performance.

Other features and packages

sleep mode

• It supports a sleep mode that turns off clocks and I/Os when no activity is needed, saving up to 95% power.

Dynamic Input Buffer Disable Feature

• The input buffer portion of the bi-directional buffer can be automatically turned off during operation without reconfiguring (reconfiguring) the FPGA.

This allows for dynamic (during operation) power down when the input buffer is not needed, for example during DDR3 idle or writes. In the case of LVDS, the user can control ON/OFF.

Nios II

• The increase in the number and speed of LEs has made it possible to install the 32-bit soft-core processor Nios II.
  Unlike microcomputers, Nios II peripherals can be freely created using LE.

package

• 3mm useful for space constrained systems ² from WLCSP (Wafer Level Chip Size Package)
  Available in FBGA packages with up to 500 user I/Os.

Product Line

Note 1: The number of PLL/ADC/TSD, etc. varies depending on the package type.
Note 2: EMIF ○ ⇒ SRAM
Note 3: ◎ in EMIF ⇒ SRAM, DDR3 SDRAM, DDR2 SDRAM, LPDD

Package List

WLCSP	MBGA/UBGA/FBGA	EQFP

Note: The same ○ is pin compatible.

How to read the product code

MAX 10 FPGA 10M08 Evaluation Kit

Compact and inexpensive evaluation kit with MAX 10 FPGA 10M08 and 80 I/O through-holes.

board photo	Block Diagram

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MAX 10 FPGA 10M50 Evaluation Kit

Evaluation kit featuring MAX 10 FPGA 10M50, Ethernet, HSMC, SPI, DDR3 and more.

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