Lowest cost CPLD ever
Combining low cost, low power consumption, and new performance, Altera's MAX ® V CPLDs offer the highest market value. With a proven non-volatile architecture and the industry's highest level of integration, MAX V delivers exciting new features while consuming up to 50% less total power than competing CPLDs.
CPLDs that offer the best value
The MAX V architecture can integrate components that were traditionally external functions, such as flash, RAM, and oscillators. Therefore, you can reduce your overall system cost by integrating a MAX V device into your design. MAX V CPLDs outperform many of their similarly priced competitors in I/O pins and logic per area. , using low-cost and green packaging technology to provide small packages as small as 20 mm2.
Reduced total power consumption
MAX V CPLDs deliver robust advanced features at half the total power consumption of comparable density competitive CPLDs.
Extends battery life with low static power consumption of only 45 uW ・Because it can be driven with a single power supply (Vcc core voltage), it is also possible to reduce BOM (parts) cost.
Manufactured on a reliable, low-cost wafer fabrication process, MAX V CPLDs employ a proven architecture while offering robust features such as:
- LE RAM: Unused logic can be converted to memory
- In-system programming (ISP): programming can be done on-the-fly, allowing in-field updates without impacting overall system operation
- User Flash Memory (UFM): Embedded flash memory that can store critical system information in non-volatile memory
table 1. MAX V CPLD Family Overview
| Features | 5M40Z | 5M80Z | 5M160Z | 5M240Z | 5M570Z | 5M1270Z | 5M2210Z |
| Number of logic elements (LE) |
40 |
80 |
160 |
240 |
570 |
1,270 |
2,210 |
| Standard equivalent number of macrocells |
32 |
64 |
128 |
192 |
440 |
980 |
1,700 |
| LE RAM (1) |
○ |
○ |
○ |
○ |
○ |
○ |
○ |
| User flash memory (number of bits) |
8,192 |
8,192 |
8,192 |
8,192 |
8,192 |
8,192 |
8,192 |
| Global clock/control pin |
4 |
4 |
4 |
4 |
4 |
4 |
4 |
| Internal oscillator |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Maximum User I/O Pins |
54 |
79 |
79 |
114 |
159 |
271 |
271 |
(1) Unused LEs can be converted to memory. The total number of LE RAM bits available depends on the instantiated memory configuration (memory mode, depth, and width).
Table 2. MAX V CPLD package and maximum user I/O pins
| package size | 5M40Z | 5M80Z | 5M160Z | 5M240Z | 5M570Z | 5M1270Z | 5M2210Z |
| 64-pin MBGA (4.5mm x 4.5mm) |
30 |
30 |
- |
- |
- |
- |
- |
| 64-pin EQFP (7mm x 7mm) |
54 |
54 |
54 |
- |
- |
- |
- |
| 68-pin MBGA (5mm x 5mm) |
- |
52 |
52 |
52 |
- |
- |
- |
| 100-pin TQFP (14mm x 14mm) |
- |
79 |
79 |
79 |
74 |
- |
- |
| 100-pin MBGA (6mm x 6mm) |
- |
- |
79 |
79 |
74 |
- |
- |
|
144-pin TQFP (20mm x 20mm) |
- |
- |
- |
114 |
114 |
114 |
- |
| 256-pin FBGA (17mm x 17mm) |
- |
- |
- |
- |
159 |
211 |
203 |
|
324-pin FBGA (19mm x 19mm) |
- |
- |
- |
- |
- |
271 |
271 |
All packages support pin compatibility between different densities.
1.BGA: Ball Grid Array (0.5 mm pitch)
2.BGA (1.0mm pitch)
3.MBGA: Micro FineLine BGA
Table 3. Key Features of MAX V
| Features | explanation |
| cost optimization | MAX V CPLDs are manufactured using a low-cost 0.18 μm manufacturing process combined with state-of-the-art low-cost packaging technology. |
| Low power consumption | MAX V CPLDs consume half the total power of competing CPLDs of similar density, resulting in less heat and longer battery life. |
| Internal oscillator | MAX V CPLDs have an internal oscillator that can be used as a simple clock source. This eliminates the need for external discrete timing devices, helping reduce BOM cost. |
|
quick power on /reset |
The fast power-on/reset of <50 μs makes MAX V CPLDs ideal for power management, power sequencing, and power monitoring of other devices on the PCB. |
| Real-time in-system programmability (ISP) | MAX V CPLDs can update different configuration images while the CPLD is running. |
| I/O function | MAX VI/O is hot-socketable and supports LVTTL, LVCMOS, PCI, and LVDS output interface standards, as well as bus-friendly options such as per-pin output enable, Schmitt triggers, and slew rate control doing. |
| green package | All packages (EQFP, TQFP, MBGA, FBGA) are available in leaded and RoHS compliant versions meeting the latest halide-free requirements. |
| Parallel flash loader | MAX V CPLDs are equipped with a JTAG block that allows you to configure external non-JTAG compliant devices such as discrete flash memory devices using the Parallel Flash Loader IP megafunction. |
| Industrial temperature range support | MAX V devices support the industrial temperature range specification of -40°C to +100°C (junction) required for various industrial and other temperature sensitive applications. |
I/O voltage flexibility
MAX V devices operate by supplying 1.8 V to the VCCINT pin. This external power supply is directly supplied to the device core, thereby keeping dynamic and static power low. The MultiVolt I/O interface (VCCIO) also provides flexibility to support various I/O standards using 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage levels.
MAX V Development Kit
The MAX V Development Kit is a hardware platform that jump-starts the development of low-cost, low-power CPLD designs.
Free tool support
MAX V can be developed with a free development tool (Quartus II Web Edition).
You can download it from the Altera website.
Resources for MAX V
Related documentation, including the MAX V datasheet, can be downloaded from Altera's website.