Introduction

SiC JFETs offer several important advantages over competing technologies, notably a low on-resistance vs. chip area, called RDS·A, and no parameter drift even with repeated high-energy transients. These, along with extremely low conduction losses and completely reliable switching under both normal and fault conditions, are crucial for circuit breakers and relays that require lifetimes of 20 years or more.

This article provides a qualitative explanation of the structure, operation, and features of ON Semiconductor's SiC JFETs.

JFET structure

Figure 1 shows a cross section of an ON Semiconductor SiC JFET. This is a vertical JFET, and in this case no voltage is applied. The three JFET terminals are labeled as source, gate, and drain in Figure 1. The PN junction at the gate and drift region forms a drain-gate diode. The other diode in the JFET is between the gate and source. Driving the gate of a JFET can be thought of as biasing a gate-source diode. Each of these diodes has a corresponding capacitance. The doping type and concentration are shown qualitatively. Each channel and gate region forms a "cell", and a single JFET can have thousands of parallel cells.

Figure 1: Cross section of a vertical JFET

There is a depletion region around the drain-gate PN junction. This depletion region has a high resistance because there are no mobile carriers. Under no bias, the depletion region is so small that current can flow freely between the source and drain terminals even when the channel is open. This gives ON Semiconductor's SiC JFETs a normally-on characteristic.

Figure 2 shows a single JFET cell with current flowing between the drain and source and a positive VDS. This positive VDS reverse-biases the drain-gate PN junction, expanding the depletion region. If VDS continues to increase until the depletion region fills the channel, the channel becomes "pinched" and the current does not increase significantly. This condition is commonly called saturation. The positive gate-source voltage forward-biases the drain-gate (and gate-source) PN junction, shrinking the drain-gate depletion region, thus counterbalancing the expansion of the depletion region due to the positive VDS, as shown in Figures 2(a) and (b) for VGS=0 and VGS>0, respectively. Applying a positive VGS is a simple way to reduce the on-resistance by about 15%, depending on the operating conditions. This significant reduction is one of the advantages of SiC JFETs in applications such as solid-state circuit breakers and relays, where minimizing conduction losses is a top priority.

Figure 2: A Qorvo SiC JFET cell with drain-source current flowing, generating a positive VDS such that (a) VGS=0 and (b) VGS>0.

The reduction in on-resistance mentioned here is due to the widening of the channel for the current route at VGS in the range of 1.8 to 2.5 V. On-resistance can be further reduced by injecting enough gate current to allow bipolar current (electrons and holes) to flow, but the benefit of this is offset by the higher gate drive power. As long as the gate current does not exceed several amps continuously during switching, there is no risk of damaging the JFET chip.

　Side note: Even when enough current is applied to the gate to cause large conductivity modulation, SiC JFETs can switch quickly: the minority carriers (holes) in the drift region either quickly recombine due to the short lifetime of the SiC, or are quickly eliminated because there is no PN junction in the current path to trap them.

Applying a negative VGS causes each depletion region to expand. With a sufficiently negative VGS, the expanded depletion region "pinches off" the channel, as shown in Figure 3 (a). VDS=5V is typically used when measuring the threshold voltage VG (th).

Figure 3: ON Semiconductor SiC JFET cell (a) VGS=VG(th), biased at VDS=5V, (b) VGS=-15V, biased at VDS=400V

In Figure 3(b), at VGS=-15V the JFET is completely off, and at VDS of 400V the depletion region has spread to the drift region where the high voltage is blocked by the drain-gate diode. As VDS is increased until the depletion region has spread to the edge of the drift region, the JFET avalanches, and further increasing VDS causes a rapid increase in the avalanche current. The power dissipation during avalanche is very high due to the high VDS, and the energy in the chip depends on the time and current spent in avalanche. ON Semiconductor SiC JFETs can withstand repeated avalanches, and all JFETs are avalanche tested during manufacturing. Of course the avalanche energy must be within the energy absorption capability of the chip, which depends on the design and chip size.

The above makes the curves in the JFET datasheet more meaningful. Figure 4 shows the output characteristics for various gate-source voltages for a UJ4N075004L8S, 750V, 4.3 mΩ SiC JFET in a TOLL (MO-229) package at room temperature (a) and at maximum operating temperature (b). A typical part has a gate threshold voltage VG(th)=-6V, and 180mA flows from drain to source at VDS=5V. A good way to think of the threshold voltage is as an indication of when the part starts to turn on rather than off. To keep the JFET completely off, the gate-source voltage must be at least 2V below the minimum threshold voltage. The minimum VG(th) for the UJ4N075004L8S is -8.3V, so the maximum keep-off voltage is -10.3V, but -12V or less is recommended.

Figure 4: Output characteristics of SiC JFET at (a) 25°C and (b) 175°C

In Figure 4, at VGS=-5V, the channel width is very narrowed by the depletion region, limiting the current flow. The current increases slightly with VDS and the JFET is in "saturation". At VGS=-4V, the depletion region narrows a bit and the channel width widens a bit, increasing the conductivity (reducing the on-resistance). The curve clearly shows the "bending" effect of the output characteristic curve, where increasing VDS widens the depletion region and the current barely follows VDS. Since the drain-source current responds strongly to changes in VGS and very little to VDS, saturation is also called active mode, and the current is gated. The boundary between ohmic and active modes is defined as VGS-VG(th) > VDS > 0 and is shown by the blue curve in each graph in Figure 4.

Increasing VGS reduces the width of the depletion region, thus widening the channel for the current route and reducing the on-resistance. Figure 4 shows the curves for a given VGS value, up to the final VGS test voltage of +2V. Note that RDS(on) is the on-resistance measured at VGS=0V or VGS=+2V. Figure 4(a) shows the output characteristics at 25°C, and Figure 4(b) shows the output characteristics at 175°C. The RDS(on) at 125°C measured at VGS=0V is 1.63 times that at 25°C, and at 175°C it is 2.18 times that at 125°C. The temperature coefficient of RDS(on), or TC for short, is mainly due to the bulk SiC material of the JFET. The RDS(on) TC should be considered when selecting the part number of SiC JFETs and determining how many to parallel.

Figure 5: ON Semiconductor Gen3 and G3n4 SiC JFETs with reverse bias

Due to the lack of a body diode, ON Semiconductor Gen3 and Gen4 SiC JFETs have unique reverse conduction characteristics. Figure 5 shows a Gen3 or Gen4 SiC JFET cell biased at various drain-source voltages with a common VGS=-15V. In Figure 5(a), VDS=-3V. Remember from all this that a negative VGS expands the depletion region and a negative VDS shrinks the depletion region. Since the difference between VDS and VGS is a few volts below the threshold voltage, the channel is completely blocked and no drain-source current flows (there is a leakage current of a few μA, but we will ignore this for now). In Figure 5(b), VDS is reduced to -9V, VGS–VDS=-6V, the VG(th) of this JFET, and a small current flows from source to drain. In Figure 5(c), VGS–VDS=-4V, 2V above the threshold voltage, and the source-drain current flows more freely.

Figure 6: Output characteristics with positive and negative VDS

The forward and reverse characteristics are summarized in Figure 6, and include negative drain-source current and voltage. ON Semiconductor SiC JFETs can limit hundreds of volts in the first quadrant (positive VDS and ID), but as we have seen, the voltage they can limit is very limited in the third quadrant. This limiting voltage is determined by the drain-gate and gate-source diode biases, and is nearly independent of temperature due to the weak temperature coefficient of the threshold voltage (TVTC). A negative VDS tends to open up the JFET channel, and a negative VGS opens the channel when approximately VDS≦VGS-VG(th). This is an approximation, since VG(th) is measured at VDS=+5V, but since we are dealing with negative VDS here, the channel widens slightly. An easy way to remember this is that the "knee voltage" of VDS is roughly equal to the voltage difference at which VGS is driven more negative than VG(th). Another way to think of the cases when reverse current can flow is to rearrange and combine VDS≦VGS-VG(th) to become VGD ≧ VG(th), as if the functions of the Gate and Source terminals were swapped.

As the current becomes more negative, and the channel expands as VDS becomes more negative, the on-resistance for reverse current relative to forward current becomes slightly lower, and the negative current vs VDS curve does not bend or saturate as it does for forward current. What happens if the source-drain current is extremely large? As shown in Figure 7, the second loop contains the gate drive and drain-gate diode, and VDS becomes negative enough to forward bias the drain-gate diode (designated DG in Figure 7) inside the JFET. This requires a very high current compared to the normal operating current of the JFET, almost causing a short circuit.

Figure 7: Drain-gate diode current causes extremely large reverse current

Such a current flowing through the internal and external gate resistors (RGJ and RG_EXT) reduces the gate-source voltage at the JFET terminals, which in turn increases the on-resistance. This tends to limit the peak reverse current. This phenomenon is more likely when the JFET chip is hot, which leads to a correspondingly higher on-resistance and lower forward voltage across the drain-gate diode. In this condition, the power losses are very high, so its duration must be short, at most a few μs.

Figure 8: UJ4N075004L8S (a) Transfer characteristics and (b) Gate current vs. voltage characteristics

Figure 8 (a) shows the transfer characteristic of UJ4N075004L8S. From the slope of the linear part of the curve, the transconductance at 25°C, 125°C and 175°C is 164 A/V, 113 A/V and 90 A/V, respectively. There is almost no crossover in the transfer characteristic curve at 25°C, 125°C and 175°C. This is because ON Semiconductor Gen4 SiC JFET has a very flat threshold voltage temperature coefficient (TVTC) of -1.8 mV/°C. The flat TVTC significantly reduces the possibility of thermally unstable hot spots on the chip during active mode operation and high current switching. This is one of the reasons why ON Semiconductor SiC JFET is highly reliable. Another reason is that there is no degradation or parameter drift due to the simple electrical structure of the JFET.

Figure 8(b) shows the gate current vs. VGS for UJ4N075004L8S, with the gate-source diode of the SiC JFET forward biased. The temperature-dependent diode "knee voltage" is obvious, and the slope corresponds to the JFET gate resistance, which is 0.4Ω for this part. Note that VGS is in the range of about 2 to 2.6V, IG is in the mA range, and the temperature is in the range of -55 to 175°C. Also, from this graph we can see that the forward voltage temperature coefficient of the JFET gate-source diode is -3.2 mV/°C. This parameter can be used to sense the temperature of the JFET chip.

Figure 9: (a) ON Semiconductor SiC JFET symbol (specific capacitance and gate resistance) (b) Capacitance vs. VDS for UJ4N075004L8S

Figure 9(a) shows a JFET symbol with the drain-gate capacitance (CDG), gate-source capacitance (CGS), and on-chip gate resistor (RG) clearly indicated. The input capacitance Ciss in the graph in Figure 9(b) is the parallel combination of the drain-gate capacitance (same as Crss) and the gate-source capacitance, and we can see that most of the input capacitance is due to the gate-source capacitance. A unique feature of ON Semiconductor Gen3 and Gen4 SiC JFETs is that there is no PN junction in the drain-source current path and therefore no body diode characteristic, and therefore no drain-source capacitance. The output capacitance Coss is the parallel combination of the drain-source capacitance and the drain-gate capacitance and is directly related to the chip size regardless of technology (JFET, MOSFET, IGBT, etc.). Since the drain-source capacitance is effectively zero, all of the output capacitance comes from the drain-gate capacitance (denoted as Crss). This is why Coss and Crss are equal in the capacitance graph in Figure 9(b).

Two final points: First, the gate charge of ON Semiconductor Gen3 and Gen4 SiC JFETs is relatively large, since Crss=Coss. During the VDS voltage transition, the entire output capacitance is charged/discharged by the gate driver. This is especially suitable for low switching frequency applications, such as semiconductor circuit protection and relays, where the switching speed needs to be easily controlled, since it only requires adjusting the gate resistor value or gate drive voltage. On the other hand, high switching frequency applications are more difficult with these JFETs due to the high gate charge. Finally, the design and layout of the gate drive loop is important.

Inquiry

If you have any questions regarding this article, please contact us below.