If you don't have a better oscilloscope...

Modern SiC switches are not just "faster," they are orders of magnitude faster than silicon for parts with similar headline ratings. This is due to the much smaller die size of SiC semiconductors, which reduces device capacitance while maintaining heat dissipation capabilities due to three times better thermal conductivity. The smaller die size of SiC vertical devices compared to 650V/1200V silicon devices is due to 10 times higher critical electric field value at breakdown. ON Semiconductor's SiC cascode JFETs use SiC JFETs that are half the size of the best available SiC MOSFETs. In test circuits where rise and fall times are measured in nanoseconds, you have to seriously consider oscilloscope bandwidth to even see the actual edge rates.

This is good news for the efficiency of switched-mode power conversion. While the voltage and current transition between high and low levels, transient power losses occur. These power losses can peak at kW, but are averaged inversely proportional to the switching frequency. However, modern converters are increasingly capable of switching at 1MHz and above, so fast switching requires these transient losses to be kept as low as possible.

Fast switching starts becoming a reality

Today, we often see edge rates of wide bandgap (WBG) devices such as SiC FETs measured at 100kV/µs or 3000A/µs or more, but is this really feasible? The series stray inductance of a TO247-based half-bridge can easily be 50nH. Since V = -Ldi/dt, 50nH drops 150V at 3000A/µs, appearing as drain voltage overshoot.

Similarly, a 100kV/µs 1A current pulse with as little as 10pF of stray capacitance on the drain causes heat dissipation problems in the heatsink. The FET's source inductance also creates voltage transients that oppose the gate drive, risking spurious turn-on. Even more troubling are problems inside the FETs, where fast transitions lead to parametric oscillations and chaotic behavior. For these reasons, SiC FETs often intentionally add an internal gate resistor to slow the edges, and it is recommended to add more external resistors to slow the on/off. .

Addressing SiC FET Cascode Issues

As shown in Figure 1, using a SiC cascode with a low-voltage MOSFET and a SiC JFET enables a fast cold-off device with virtually zero gate-to-drain capacitance CGD, thus partly solving the problem. can be mitigated.

External gate resistors R(ON) and R(OFF) can control the edge rate to reduce dV/dt and di/dt. This is a very practical solution and can be used to upgrade existing systems using standard Si MOSFETs and IGBTs to be more efficient while keeping the existing gate drive circuitry. Using an external gate resistor to slow down the edge rate introduces a delay between the output of the control IC and the switch gate, limiting the minimum on-time and thus limiting the control range and operating frequency. . It also slows down the response time to shutdown commands in the event of a failure. This is a serious problem for new designs that need to operate at high frequencies to take full advantage of WBG.

Realizing high speed cascode

Recent studies have shown that "unbraking" the SiC JFET cathode with faster JFETs and a low value external gate resistor can improve switching speed and efficiency while adequately limiting voltage overshoot using a simple RC snubber. While one might think of simply shifting losses from the FET to the snubber, tests have shown that a much smaller snubber can still provide voltage limiting effectiveness. The JFET improvements result in a 50% reduction in reverse recovery charge (Qrr), reducing turn-on losses compared to the UJ3C generic device.

This "FAST" device from ON Semiconductor forms part of the UF3C series and can typically be used with a snubber resistor of 5-10 Ω and a capacitor of 47 pF or less. Actual recommended values will vary depending on the device type and end application, with circuits such as hard-switched active rectifiers and totem pole PFCs working best. A good rule of thumb is to set the capacitor at about 3 times the COSS of the device. When upgrading an existing design, the location of the snubber often already exists and the value using UF3C parts is usually much smaller physically and of course less expensive.

Figure 2 shows a comparison of the total switching losses of various 1200V/35mΩ class devices in a TO-247 package. The UF3C120040K3S with a gate resistor of 33Ω and snubbers of 330pF and 5Ω shows excellent results over the entire load range and even allows for a simpler driver with only one Rg.

Figure 3 shows the loss measurements of the snubber resistor of UF3C120040K3S. This loss is only a small fraction of the total switching loss because the required capacitance is very small.

With the new UF3C series of SiC cascodes, you can get the efficiency benefits that high-speed switching offers without the risk of overshoot voltage stress in small snubbers. The fact that the device is compatible with a wide range of Si and SiC gate drive voltages and is also guaranteed avalanche rated is a bonus.

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