Considering the change in parameters of SiC cascode JFET with temperature

Power transistors have several important parameters (FoM), such as drain-source resistance Rds and switching losses Eoss. These numbers are usually given in the datasheet, but it is not always clear how these numbers change with temperature. These numbers are also affected by the die area, resulting in FoMs such as RdsA and Rds over area.

Of course, these numbers are "typical" and are generally given for an operating temperature of 25°C. And these numbers are derived from the Rds(on) at these "typical" conditions, and do not take into account how Rds(on) changes with temperature, and more importantly, how that change varies from architecture to architecture.

This can be seen clearly by looking at a device such as ON Semiconductor's 650V SiC cascode JFET device UF3C065040K3S. This device has a documented Rds(on) of 52mΩ max (42mΩ typical) at 25°C. Comparing this to a 650V superjunction MOSFET with an Rds(on) of 45mΩ max (40mΩ typical), the superjunction device appears to perform better at this particular FoM. However, as Figure 1 shows, things change dramatically as temperature increases. Approaching 150°C, the Rds(on) of the superjunction element reaches 96mΩ, while the SiC cascode element only reaches 78mΩ. In fact, even at 175°C the Rds(on) of the SiC device is only 78mΩ, well below the Rds(on) of the superjunction device.

It is clear from Figure 1 that the increase in Rds(on) of the SiC cascode device is much lower than that of the superjunction MOSFET.

Related to this lower conduction loss, SiC cascode JFETs dissipate less power at higher temperatures, as much as 30% less power than superjunction devices at 150°C. Since the amount of power dissipated also contributes to the increase in temperature, less loss means a lower overall temperature and therefore a lower Rds(on) figure. Lower Rds(on) also means that more current can be carried, which is even more significant in the applications where these devices are used. Another benefit of this FoM is that the die area can be minimized, which reduces switching losses and body diode losses.

The low rate of increase in Rds(on) over temperature in SiC cascode JFETs is a result of the high doping levels used in SiC, which reduces the degradation of electron mobility that occurs with increasing temperature in all semiconductor materials. In addition, with benefits in terms of gate charge and other FoM, engineers will find that using SiC cascode JFETs can enable significant system-level design improvements and cost savings.

Datasheets can tell you how a device will perform under different conditions, but it is important to understand the effects of temperature and not generalize between different types of devices.

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