Key role of cascode in SiC success

Cascodes have proven to be a very useful structure since they were invented in the days of vacuum tubes to overcome the Miller effect. Of course, the Miller effect was discovered by John Milton Miller in 1920, but vacuum tubes did not eliminate it. The Miller effect continues to this day as a result of the parasitic capacitance inherent in all transistors. Limiting high frequency performance limits the switching speed of today's power conversion circuits.

As designers seek to leverage the energy efficiency, thermal performance, and durability improvements of silicon carbide (SiC) technology into switching power supplies, converters, and inverters for all types of equipment, cascode is a highly valuable It has once again been proven to be something. A cascode of a low-voltage silicon MOSFET and a high-voltage SiC JFET in the same package can be controlled using a normal MOSFET gate drive signal generated by a normal MOSFET gate driver. Also, JFETs are normally on devices, whereas cascodes are normally off, making them suitable for power supply circuits. This allows you to take advantage of the superior body diode performance of SiC cathodes compared to conventional SiC MOSFETs.

However, cascodes effectively avoid the Miller effect by stabilizing the drain voltage of the input transistors, not by eliminating the parasitic effects inherent in the transistors themselves.

Silicon MOSFETs, being low voltage devices, have a low RDS(ON) that minimizes their impact on energy losses, while SiC JFETs still have the advantage due to their high switching performance and good RDS(ON) for rated voltage and rated current. On the other hand, there can be a large difference between the capacitance of the MOSFET (CDS Si) and the capacitance of the JFET (CDS SiC). This can cause some problems when using cascodes in very high voltage switching circuits.

A large CDS SiC relative to the CDS Si can cause high voltages to appear at the drain of the Si MOSFET when both devices are off, exceeding the breakdown voltage of the MOSFET and potentially causing the device to fail. Additionally, a finite value of CDS SiC can pass current pulses that can cause spurious turn-on of the JFET, preventing zero voltage switching (ZVS) in soft switching topologies. It can also cause "divergent oscillations" during high current turn-off, which can destroy the JFET.

There are essentially two ways to address the imbalance: increase one or decrease the other. Huang et al. proposed adding capacitance and demonstrated improved high current turn-off behavior. The location and value of this added capacitance is critical.

ON Semiconductor is addressing this challenge through one of the most promising technologies for reducing the capacitance of SiC JFETs. ON Semiconductor's vertical channel structure, shown in Figure 2, allows the CDS SiC to be made virtually negligible. Leveraging this technology, SiC cascodes can come even closer to the performance of an ideal switch.

Figure 2: ON Semiconductor vertical channel architecture makes the CDS of SiC JFETs negligible

In order to further improve the performance of the SiC cascode, we have devised ways such as stacking the MOSFET and JFET dies. SiC JFET manufacturing has a high yield per wafer and allows for cost-effective cascode construction even with two devices stacked on top of each other. Stacking provides further cost savings while further reducing inductance inside the package, allowing for greater speed and efficiency.

SiC cascodes are already playing a leading role in realizing the benefits of silicon carbide in critical power conversion applications such as renewable energy generation, transportation, consumer technology and smart industry. Nearly 100 years after its inception, SiC cascodes are still helping overcome engineering challenges, and there is still room to evolve and improve these critical devices.

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