Why not use an FPGA with a fast boot time?

table of contents

Why not use an FPGA with a fast boot time?
Is there a configuration for the flash-based FPGA?
Example of time from power-on to when the device's I/O becomes usable (comparing two 6K LE FPGAs)
Calculation of PolarFire startup time as mentioned at the beginning
Summary

One of the reasons Microchip FPGAs are chosen is their fast boot time.
Even customers who normally use FPGAs from other vendors sometimes choose Microchip FPGAs for products with strict system startup time requirements.
For example, the boot time of the currently popular PolarFire is Approximately 70.06ms (Max) ~1.93ms (Min) This is the result.

if,
- End users require shorter system startup times, and we are struggling with the current FPGA startup times.
- I want to be able to quickly restore power after it has gone out for some reason.
- The circuit board's power is periodically turned off to conserve energy, and it needs to be quickly started up to establish communication with other circuit boards.
In such cases, we highly recommend trying Microchip FPGAs to shorten FPGA startup time.

Is there a configuration for the flash-based FPGA?

Microchip FPGAs are flash-based (non-volatile).
Once the device is programmed, the circuit design remains even after the power is turned off, so there is no configuration required after power-on.

Similar devices include FPGAs from other FPGA vendors that do not require a configuration ROM and can be used as a single chip,
In the case of SRAM-based FPGAs, time is required after power-up to configure the device from the Flash area to the SRAM area.

Example of the time from power-on to when the device's I/O becomes usable (comparing 6K LE FPGAs)

6K LE of FPGA When comparing them
MicrochipIGLOO2 M2GL005: VDD rise time (50us ~ 100ms) + 2.587ms
FPGAs from other FPGA vendors (examples): about 76.6798ms That's all.
This is the result.

MicrochipIGLOO2 boot time:
- The VDD rise time can be set by the user between 50us and 100ms.
The time it takes for VDD to reach the minimum voltage level and enable I/O output will vary depending on your device.
Please refer to "Table 122 • VDD Power-Up to Functional Time"​in "UG0448: IGLOO2 FPGA High Performance Memory Subsystem User Guide".
https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/igloo-2-fpgas#Documentation

Calculation of PolarFire startup time as mentioned at the beginning

The breakdown of the calculation, which takes approximately 70.06 ms (Max) to 1.93 ms (Min), is as follows:
Max
tPUFT
= tFAB_READY(cold) + tCALIB
= 7.87ms(Max) + 62.19ms(Max) = 70.06ms * VDDI ramp time slowest 50ms
Min
tPUFT
= tFAB_READY(cold) + tCALIB
=0.95ms(Min) + 0.98ms(Min) = 1.92ms * VDDI ramp time is now 0.2ms

For details, please refer to the latest version of the documentation.
PolarFire FPGA Datasheet
・PolarFire Family Power-Up and Resets User Guide
Please refer to the following.
https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/polarfire-fpgas#Documentation

The startup sequence diagram can be found in the "5.9. Power-Up to Functional Timing" section of the "PolarFire FPGA Datasheet".
Sections 2.2. Device Boot and 2.3. Design and Memory Initialization in the "PolarFire Family Power-Up and Resets User Guide"
It is described there.

The startup time is calculated using the following formula.
TPUFT = TFAB_READY(cold) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB)
TWRFT = TFAB_READY(warm) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB)

*Regarding max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB)
"max" will use the larger of (tPCIE + tXCVR + tLSRAM + tUSRAM) or tCALIB.

* When powering on, refer to the cold value; when asserting the DEVRST_N pin, refer to the warm value.

 
The parameters are as follows, according to the "PolarFire FPGA Datasheet":

・TFAB_READY(cold)
         Table 5-97. Cold Boot
         Time when fabric is operational - TFAB_READY(cold)
         0.95(Min) 4.41(Typ) 7.87(Max) ms

・TCALIB
Table 5-100. I/O Initial Calibration Time (TCALIB)
VDDI ramp time slowest 50ms: 62.19ms (Max) ~ 41.62 (Min)
VDDI ramp time 0.2ms minimum: 2.63ms (Max) ~ 0.98ms (Min)

* Please prioritize the figures in the latest documentation for your reference.


• The number of "TPCIE + TXCVR + TLSRAM + TUSRAM" components will increase or decrease depending on whether they are used or not in the customer's design.
Please check the compilation report on Libero SoC.
If the value is greater than TCALIB, please use this value.
Under Generate Design Initialization Data, Design_Initialization_Data_Report.txt

Example: an5021 Devie side design

summary

If you're experiencing problems with the waiting time between powering on and the product becoming operational, please consider Microchip FPGAs!

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