What is PCIe SW

PCIe for Peripheral Component Interconnect express. I'm sure many of you have seen this name on motherboard connectors. Do you know PCIe Switch that uses this standard?

PCIe SW was originally a standard for accessing memory from the CPU, but now it is often used for servers and storage. Even within the industry, which has not shown interest in high-speed communication, the advent of high-precision cameras and 5G has inevitably attracted attention to high-speed communication as the amount of data increases. In this article, we will explain in order while focusing on the basic functions and features of PCIe SW.

Memory space and configuration space of PCIe SW

In Part 2, we will explain the memory space and configuration space, which are the axis of communication contents when communicating with PCIe SW by TLP. In the previous article, I explained that PCIe SW is mainly for the function of distributing (switching) data sent from the host to downstream end devices. In order to distribute the data, it is necessary to set the host to access the EP via PCIeSW. The PCIe SW uses a Transaction Layer Packet (TLP) to configure these settings.

Items set by this TLP include memory space, configuration space, I/O space, and message space. The four spaces are briefly summarized below.

​-Memory Space: This is the area used by the CPU to read and write data. It is responsible for transferring the actual data.

-Config space: Used to set communication parameters, set lane width, notify communication status, and notify TLP reception errors.

- I/O Space: Used to transfer data to and from I/O mapped locations. It exists primarily to ensure compatibility with legacy devices.

- Message Space: Used for requesting interrupts, etc. PCI and PCI-X had dedicated lines.

In Part 2, I briefly explained the memory space and configuration space in TLP of PCIeSW. In the third article, I will continue to explain the basics of PCIeSW.

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