Nios® II Beginner's Guide - Nios® II Simple Tutorial

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Design FPGA/CPLD/ASIC Intel

This "Nios® II Getting Started Guide" series is for users new to the Nios® II processor.

explanation

< Tool version: for Ver.18.1>

This document is for users who have a Cyclone® V GX starter development kit, and shows the procedure for creating a simple Nios® II design and performing a simple operation check on the development board.

In addition, by comparing general embedded systems and Nios® II systems and making them relevant to the design development flow, both embedded system engineers and logic design engineers can understand each other.

This material is the same as the exercise manual used in the "Nios® II Introductory Trial Course" seminar held by our company.

<Tool version: For Ver.17.0/Ver.14.0>

This document is a tutorial-style summary of Nios® II system generation using the Intel® Quartus® Prime software and the Nios® II Software Build Tools for Eclipse (Nios® II SBT).
Using simple hardware and software, you can understand the minimum necessary development flow until you check the operation.

The hardware configuration of the design used for illustration in this document consists only of the Nios® II core, JTAG UART, on-chip memory, and PIO components for 8-bit outputs for LEDs. The software is a very simple description that just blinks an LED.

While looking at this document, you can create a design from scratch. The sample design is after the design is completed.