1st Implementation of USB 3.0 interface using FPGA

≪Contents≫

≪USB 3.0 Solution Overview≫

USB 3.0 is the next-generation USB standard widely used as an interface for connecting PC peripherals. It is also called "Super Speed mode" and enables high-speed data communication of 5 Gbps, which is more than 10 times the communication speed (480 Mbps) of the conventional "High Speed mode (USB 2.0)". In addition, USB 3.0 has backward compatibility, and USB products for conventional "High Speed mode", "Full Speed mode (USB 1.1/12 Mbps)", and "Low Speed mode (USB 1.0/1.5 Mbps)" are also available. You can use it as is.
In recent years, the amount of data has increased, and how to transfer that large amount of data at high speed has become a problem. It has been.

<<Realization of USB 3.0 interface using FPGA>>

It is also possible to implement a USB 3.0 interface using ASSPs, ASICs, etc. However, ASSP has limited functions and lacks versatility. In addition, ASIC has major issues such as development period and high risk.
Therefore, we propose to implement a USB 3.0 interface using Altera's FPGA. By using FPGA, the design inside the device can be rewritten according to the user's specifications, so the versatility that was the problem with ASSP is solved, and the problems with ASIC, such as development time and high risk. is also greatly improved.
There are roughly two ways to implement a USB 3.0 interface using Altera's FPGA (see Fig. 1). The first method is to use an FPGA with a built-in transceiver of 5Gbps or higher. In this method, the FPGA acts as a transceiver in "Super Speed mode", eliminating the need for an external PHY for the USB 3.0 interface. But you need to provide an external PHY for USB 2.0 interface. Since there is no need to connect the PIPE III interface on the board, it has the advantage of making board design easier. There is a disadvantage that it is not suitable for
The second method is to use a low-cost FPGA and an external PHY for the USB 3.0 interface. Since it is necessary to connect the PIPE III interface on the board, there are disadvantages such as an increase in the board area and the number of wiring, but compared to the above-mentioned method using a high-end FPGA, the cost is suppressed and it is suitable for mass production. It can be said that there are

≪USB 3.0 Board using low-cost FPGA≫
You may think that the new standard is uneasy in terms of cost and performance. With no actual track record, no matter how much you propose, it will be a rice cake in the picture. Therefore, in order to propose the USB 3.0 interface as a low-cost solution at the actual machine level, we have produced a board that realizes the USB 3.0 interface using a low-cost FPGA.
By incorporating solutions other than USB 3.0, such as DDR2 / MRAM / HSMC, etc., into the specifications of the board, it has excellent expandability and can be verified according to various cases (block diagram of the board is as shown in “Fig.2”).

Fig.2

In addition, the PHY for USB 3.0 is TUSB1310 from Texas Instruments, the IP for USB 3.0 programming to FPGA is from Inventure, and the connector/cable for USB 3.0 is from Hosiden. Thank you for your cooperation.

Next time, we will introduce the DDR 2 interface, which is often used as a memory interface mounted on this board. Full of useful hints that will not fail in board design! In the final installment, we will introduce a USB 3.0 solution using this board. We will reveal the secret that enabled that next-generation interface to be realized at low cost.

Part 2: How to verify the design of DDR 2?  
Part 3: Design and verification of USB 3.0