intel^®Agilex™ FPGAs Introduces the internal structure of the and its functions.

Agilex™ FPGAs When you open the package, you can see that it contains several dies and has a multi-die structure. In the center is the FPGA fabric and around it are various tiles for transceivers. EMIB (Embedded Multi-Die Interconnect Bridge) connects between FPGA fabric and various tiles.

The central FPGA fabric has the same configuration as traditional FPGAs, such as logic modules, DSP, memory, ARM processors, and general-purpose I/O, and uses the optimum process for digital circuits.

Each peripheral tile has a high speed transceiver and associated hard macros, using the best process for each tile.

The EMIB, which connects between the FPGA fabric and each tile around it, is a tiny silicon chip embedded inside the package substrate. High-speed transmission of signals between the FPGA fabric and peripheral tiles.

The FPGA fabric uses the 3rd generation SuperFin process, an improvement on ^Intel 's 10nm process for even better performance.

The operating frequency has been greatly improved by adopting the ^Intel® Hyperflex™ FPGA architecture, which inserts Hyper-Registers into the entire interconnect wiring and the inputs of all functional blocks. In order to balance performance and power consumption, the standard power products automatically optimize the core voltage according to individual device characteristics with SmartVID, and the low static power products reduce power consumption with a fixed core voltage as low as 0.8V. To do.

As a feature of the FPGA fabric, logic modules contain up to 3+ million LEs.

The DSP is a variable precision DSP block with a floating point unit, with a maximum performance of 40TFLOPs. The on-chip memory is equipped with a maximum of 300MB or more.

The processor is powered by a quad-core 64-bit Arm Cortex-A53 up to 1.41GHz.

As an interface with external memory, it is equipped with a hard memory controller that supports DDR4 and DDR5, and as general-purpose I/O, it is equipped with a total of over 1,000 GPIOs.

There are four types of tiles for Agilex™ FPGAs: E-tiles, F-tiles, P-tiles, and R-tiles.

E-tiles and F-tiles are networking and communication tiles. Equipped with ultra-high-speed transceiver and hardware IP such as Ethernet such as 100G and 400G and PCI Express.

P-tiles and R-tiles are the best tiles for connecting to processors. It features high-speed transceivers and hardware IP for PCI Express and processors. The hardware IP is a design optimized for the application from transistors, so it consumes less power than configuring the same function with FPGA blocks, but the function is limited to the intended use. has the advantage of not consuming FPGA block resources.