Pin connection guidelines

Pin Connection Guidelines (All Devices Except Agilex™)

*Intel® Agilex™ familyhere

Schematic Review Worksheet Top Page

Arria® V GT, GX, ST, and SX Device Family Pin Connection Guidelines

Arria® V GX, GT, SX, and ST Device Schematic Review Worksheet

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● Refer to the datasheet and apply the recommended power supply voltage.

● Establish a measurement point near the FPGA

・Be ready to measure the power supply in case of trouble

● Refer to Power & Thermal Design & Debugging Guidelines​

● When not using all GXBs (transceivers) on the same side

・VCCR_GXB[L,R], VCCT_GXB[L,R], VCCL_GXB[L,R], VCCH_GXB[L,R], VCCA_GXB[L,R] can be connected to GND.

● Number of decoupling capacitors

・Estimate with reference to the PDN tool​

・For a more detailed estimate, use a dedicated tool

<Reference>

　　Power Delivery Network (PDN) Analysis Tool

　　Part 9 Confirmation and Review of Capacity in FPGA Power Supply Design

● When configuring in Active Serial (AS) mode

・ VCCPGM is 3.0 V or 3.3 V

● Power sequence

See this document (Arria V GX, GT, SX, and ST Power-Up Sequence) for more details.

MSEL Pin Settings

Inserting pull-up/pull-down resistors⁽¹⁾⁽²⁾

unnecessary

(see documentation here)

Arria V SoC via HPS

● DCLK

・Recommend inserting damping resistor (minimum 0Ω) 10-50Ω

- In AS mode, take care of the trace length (see the document below)

　　"Trace Length and Loading Guidelines"

● nCONFIG, nSTATUS

・Pull up to VCCPGM via 10kΩ resistor

● CONF_DONE

・Pull up to VCCPGM via 10kΩ resistor

・Do not connect to the LED as it is.

- Due to lack of drive current, it may not light up without applying FET

● When FPGA is cascaded, nSTATUS and CONF_DONE are common and pulled up.

- INIT_DONE is pulled up individually (only if used)

● nCE

・Pull down via GND connection or 10kΩ resistor

・This signal determines whether the FPGA is cascaded.

● When using nCEO, pull up to VCCPGM through a 10kΩ resistor.

● Check Point

・It is recommended to insert a 0Ω damping resistor for TCK.

- To support cases where writing is not possible due to problems with the clock system

● Pin processing

・TCK: Pull down via 1kΩ resistor (Pull down via 1kΩ resistor even when not used)

・TDI: Pulled up to VCCPD via 1kΩ to 10kΩ resistor (pulled up via 1kΩ resistor when not used)

・TMS: Pulled up to VCCPD via 1kΩ to 10kΩ resistor (pulled up via 1kΩ resistor when not used)

・TDO : No pull-up/pull-down (open when not used)

● Assign to p-channel when using single-ended clock

(This is a limitation when using the ALTCLKCTRL buffer because n-channel does not directly ride on the global clock.)

● Pay attention to AC/DC coupling when inputting differentially

pin name

comment

RREF_TL

RREF_BR

Pull down through a 2kΩ resistor if using PLL (resistor accuracy is ±1%)

● Connect to GND when transceiver is not used.

・Connect the clock (REFCLK_*) to GND

・RX (GXB_RX_*, GXB_REFCLK_*) is connected to GND

・TX (GXB_TX_*) is floating

● AC/DC coupling

・Adjust to I/O Standard

Arria V SoC Pin Names

comment

CLOCKSEL[1:0]

Pull up or pull down to VCCIO voltage through a 4.7 kΩ to 10 kΩ resistor

BOOTSEL[2:0]

Pull up or pull down to VCCIO voltage through a 4.7 kΩ to 10 kΩ resistor

HPS_nRST (bidirectional pin)

Pull up to VCCRSTCLK_HPS voltage through 1kΩ to 10kΩ resistor

SDMMC

Pulled up through a 10kΩ resistor

If you use QSPI > 128Mbit, you need to use an IC with reset (Bootrom software works in 3-byte mode, so you can't boot)

[Reference] CV SoC and AV Soc QSPI Boot (From RocketBoards.org)

pin name

comment

CLKUSR

If not used as a function pin and not used as a user I/O pin,

Set Reserved Pin = "As output driving ground" in Quartus Prime and connect to GND

 DEV_OE

DEV_CLRn

PR_REQUEST