explanation

This document presents a hardware and software implementation using the Vectored Interrupt Controller Core (VIC).

By using VIC, interrupt control with faster response time can be realized.
In addition, VICs can be daisy-chained to control more than 32 interrupts, and many other enhancements such as priority modification and non-maskable interrupts are possible.

Document

content

1.First of all
2. Applicable Conditions
3. System configuration
3-1. Qsys settings
3-2. Peripheral settings
3-2-1. VIC settings
3-2-2. Nios II settings
4. Implementation on Nios II SBT
4-1. BSP settings
4-2. Interrupts when interrupt nesting is not allowed
4-3. Interrupts when enabling interrupt nesting (different register sets)
4-4. Interrupts when enabling interrupt nesting (same register set)
4-5. Interrupt settings when interrupt nesting is enabled even with the same register set
5. SOFTWARE MODIFICATIONS
5-1. Differences in description
5-2. Change of description

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