explanation

This "Nios® II Getting Started Guide" series is for users new to the Nios® II processor.

Platform Designer comes standard with the I2C Slave to Avalon®-MM Master Bridge Core. By using this IP core, you can easily implement an I2C slave connected to a memory inside an FPGA. .

This document introduces how to implement the same function as I2C BUS EEPROM in FPGA using address stealing function of I2C Slave to Avalon®-MM Master Bridge Core and On-Chip Memory (RAM and ROM) Core. .

Document

nios2_i2c_slave_v171_r1__1.pdf

Tool version: Documentation for Ver 17.1

sample file

i2c_slave_sample__1.zip

Tool version: Sample design and sample code for Ver 17.1

The example files include FPGA designs (QAR files) and source code (C files).
[FAQ] Intel: What are QAR files for?

Click here for recommended articles/materials

Nios® II related articles and resources
Intel® FPGA Development Flow/FPGA Top Page

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Nios® II FAQs
Intel® FPGA FAQs

Click here for recommended seminars/workshops

Nios® II Introductory Trial Course <Free>
Custom microcomputer design trial ~Experience embedded design using MAX® 10 FPGA! ~ <free>