explanation

This "Nios® II Getting Started Guide" series is for users new to the Nios® II processor.

Avalon® I2C (Master) Core is prepared in Platform Designer as standard, and this IP core can perform I2C communication under the control of Nios® II.

By default, this IP core connects to an Avalon® Memory Mapped Interface (Avalon®-MM) port and is implemented to communicate using register operations, including data. ST), and by connecting DMA, FIFO, etc. to the Avalon®-ST port, it is possible to control Nios® II with minimal register operations. This document describes that method.

Document

nios2_i2c_master_v171_r1__1.pdf

Tool version: for Ver 17.1

sample file

i2c_master_sample__1.zip

Tool version: Sample design and sample code for Ver 17.1

The example files include FPGA designs (QAR files) and source code (C files).

[FAQ] Intel: What are QAR files for?

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Nios® II related articles and resources
Intel® FPGA Development Flow/FPGA Top Page

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Nios® II FAQs
Intel® FPGA FAQs

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Nios® II Introductory Trial Course <Free> 
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