explanation

An Intel® SoC FPGA has an ARM® core and FPGA bused together inside the device. Since it is connected within the device, it is expected to eliminate the insufficient transfer rate between the processor and FPGA and reduce the mounting area on the board.

This document is intended for users who have the Cyclone V SoC FPGA development kit "DE0-Nano-SoC Kit / Atlas-SoC Kit" or "DE10-Nano Kit" to experience the development flow of SoC FPGA hardware and software. can. Users who do not have a development kit can borrow a development kit and try it out at "Experience at your desk! Intel® SoC FPGA Seminar In a Box".

This is the same as the exercise manual included in "Experience at your desk! Intel® SoC FPGA Seminar In a Box".

* The content for Ver.20.1 and Ver.18.1 is based on the assumption that it will be performed on a PC with Windows 10 installed. Please use the contents for Ver.17.1 when using in the environment before Windows 7.

* Arm® Development Studio (Arm® DS) is used for Ver.20.1, and Arm® Development Studio 5 (DS-5™) is used for Ver.18.1 and Ver.17.1. Customers considering new development should use Ver.20.1.

Document

Exercise Manual (Ver.20.1 / Rev.3)
Exercise Manual (Ver.18.1 / Rev.2)
Exercise Manual (Ver.17.1 / Rev.4)

exercise data

Practice data (Ver.20.1)
Practice data (Ver.18.1)
Practice data (Ver.17.1)

Click here for recommended articles/materials

SoC FPGA related articles and resources
Intel® FPGA Development Flow/FPGA Top Page

Click here for recommended FAQ

SoC FPGA related FAQs
Intel® FPGA FAQs

Click here for recommended seminars/workshops

SoC Startup Trial <Free>

Experience at your own seat! Intel® SoC FPGA Seminar In a Box

You can rent an evaluation board equipped with Intel® SoC FPGA for two weeks, and you can easily experience the development flow of Intel® SoC FPGA at your desk. We also provide development tools, practice data, and manuals, so you can practice at your leisure.

Experience at your own seat! Intel® SoC FPGA Seminar In a Box