explanation
This document demonstrates how to program Nios® II in a 512Mb Quad SPI Flash memory implemented in a MAX® 10 FPGA Development Kit and program Nios® II via an Altera Generic QUAD SPI Controller implemented in a design within a MAX® 10 device. This document describes how to boot. You can refer to it as an example design for using the Quad SPI Flash memory as external non-volatile memory to store the Nios® II program.
Document
Nios II boot method from Quad SPI Flash memory MAX 10 FPGA Development Kit (Ver.15.1)
sample design
Tool version: Sample design for Ver.15.1
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Nios® II related articles and resources
Intel® FPGA Development Flow/FPGA Top Page
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Nios® II Introductory Trial Course <Free>
Custom microcomputer design trial ~Experience embedded design using MAX® 10 FPGA! ~ <free>