Today most devices are CMOS, but before the advent of high speed CMOS most devices were TTL.
At that time, CMOS existed, but it was very slow, for example the metal gate CMOS4000 series, and was only used where low power requirements were high.

Figure 1 shows the static characteristics of the TTL (7400) output.
The Low side (Pull Down) and High side (Pull Up) were asymmetrical, and the concept of drive capability was also different from today.
The low side has a small output resistance up to a certain current, and the high side is about 100Ω.
Therefore, it was meaningless to insert a damping resistor, which is often used in current CMOS, and there was no such concept.

Figure 2 shows the current CMOS static characteristics and Bergeron analysis results.
Low and High are almost symmetrical, and both can be regarded as straight lines.
A 24mA driver with a 22Ω damping resistor inserted gives a nearly clean response.

Figure 3 is a Bergeron analysis of TTL with Z0=50Ω and Figure 4 is its time response.
The horizontal axis is normalized by the one-way propagation delay τ of the line.
The low-to-high rise has an initial step around 2.3V and then slowly approaches the final value. From high to low, there is a negative overshoot, but it falls at once.

Figures 5 and 6 are also for Z0 = 80Ω.
The rise is slightly stepped, but better than 50Ω.

Figures 7 and 8 are also for Z0 = 100Ω.
Finally, I was able to stand up.

Figures 9 and 10 are also for Z0 = 120Ω.
It is difficult to make a board with Z0 = 120Ω, and as shown in Fig. 10, the amplitude at the beginning of the rise is higher than the final value when Z0 ≤ 100Ω. , takes time to settle to a steady-state value. We can see that there is a difference between the last amplitude from Low to High in Figure 10 and the first amplitude from High to Low.

Figure 11 shows the results of analyzing the rising waveform in Figure 10 up to 135τ. It first rises to around 3.7V, then becomes high impedance due to the reverse bias of the base-emitter of the emitter follower described above, and gradually approaches the final value of 3.5V.

The output characteristics were obtained by plotting from the datasheet, and may differ slightly from the data of the actual circuit. The low level rises by the amount falling before reaching the steady state value. TTL had little margin especially on the Low side, so I had to be careful.

Figure 12 shows the TTL schematic for reference. Consider why the phenomenon in Figure 11 occurs.