Learn about the internal structure and functionality of Altera® Agilex™ FPGAs.

When you open the Agilex™ FPGA package, you will see several dies inside, forming a multi-die structure. The FPGA fabric is in the center, surrounded by various transceiver tiles. The FPGA fabric and the various tiles are connected by an EMIB (Embedded Multi-Die Interconnect Bridge).

The central FPGA fabric contains the same components as conventional FPGAs, including logic modules, DSPs, memory, ARM processors, and general-purpose I/O, and uses a process optimized for digital circuits.

Each peripheral tile contains high-speed transceivers and associated hard macros, and uses the process that is best suited for that tile.

The EMIB, which connects between the FPGA fabric and each tile around it, is a tiny silicon chip embedded inside the package substrate. High-speed transmission of signals between the FPGA fabric and peripheral tiles.

The FPGA fabric uses Altera's third-generation SuperFin process, an improved version of the 10nm process, further improving performance.

The Altera® Hyperflex™ FPGA architecture, which inserts Hyper-Registers into the entire interconnect wiring and the inputs of all functional blocks, has significantly improved the operating frequency.To achieve both performance and power consumption, standard power products use SmartVID to automatically optimize the core voltage to match individual device characteristics, while low static power products reduce power consumption by using a low fixed core voltage of 0.8V.

As a feature of the FPGA fabric, logic modules contain up to 3+ million LEs.

The DSP is a variable precision DSP block with a floating point unit, with a maximum performance of 40TFLOPs. The on-chip memory is equipped with a maximum of 300MB or more.

The processor is powered by a quad-core 64-bit Arm Cortex-A53 up to 1.41GHz.

As an interface with external memory, it is equipped with a hard memory controller that supports DDR4 and DDR5, and as general-purpose I/O, it is equipped with a total of over 1,000 GPIOs.

There are four types of tiles for Agilex™ FPGAs: E-tiles, F-tiles, P-tiles, and R-tiles.

E-tiles and F-tiles are networking and communication tiles. Equipped with ultra-high-speed transceiver and hardware IP such as Ethernet such as 100G and 400G and PCI Express.

P-tiles and R-tiles are the best tiles for connecting to processors. It features high-speed transceivers and hardware IP for PCI Express and processors. The hardware IP is a design optimized for the application from transistors, so it consumes less power than configuring the same function with FPGA blocks, but the function is limited to the intended use. has the advantage of not consuming FPGA block resources.