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Hello everyone, I'm Motsu.
Currently, I am making a clock using FPGA in my training.
The design was created in both Verilog HDL and VHDL.
First of all, it was completed in Verilog HDL.
I thought that VHDL would be difficult, but my senior told me, "If it's written in Verilog, just change it!"
I was relieved that I could do it right away!
However, when I actually tried it, it was full of errors as expected...
I thought, "It can't be that easy," and decided to review it one by one.
If you look closely, you will find that there are many mistakes.
So, this time, I will introduce some of the grammatical differences between Verilog HDL and VHDL that I misunderstood in my training.
・ Even if you write multiple lines, you don't need begin...end! ?
・ The way to comment out is different! ?
Rise processing with clock
In Verilog, when processing is performed at the rising edge of the clock,
always @ (posedge clk)
I wrote,
In VHDL,
process ( clk ) begin
if ( clk 'event and clk = '1' ) then
I have to write!
I've been writing only Verilog HDL for a while, so I've completely forgotten about it, and I was wondering if I should just write it on the sensitivity list. (lol)
Even if you write multiple lines, you don't need begin...end! ?
For example, in Verilog HDL, begin...end was required when the statement description spanned two or more lines.
VHDL is written differently.
We put begin...end after the process statement, but we need then after the if statement.
You need an end if if that if statement ends!
How to comment out is different! ?
In Verilog HDL,the comment out was "//" (double slash), and "/* ... */" for multiple lines.
Commenting out in VHDL 1993 is "--" (double hyphen), and when commenting out multiple lines, all lines must be preceded by a double hyphen.
I thought it was a little troublesome, but there was an easy way! !
By clicking the Toggle Comment button (red circle below) in the Quartus II text editor tool bar, you can comment out all the selected lines at once.
Moreover, I was told by a senior later
In VHDL-2008, it seems that /* … */ in Verilog HDL can now be commented out.
Symbols cannot be used in logical operators! ?
When writing logical operators,
Verilog HDL is written with "symbols", but VHDL cannot use symbols as shown in the table below.
|
logical operator |
Verilog HDL |
VHDL |
|
logical negation |
! |
not |
|
Logical AND |
&& |
and |
|
disjunction |
|| |
or |
Representing Numbers in If Statements
In Verilog HDL, for example, 4'd9 is used to represent a 4-bit 9 in decimal.
but,
I thought, "In VHDL, there was no such way of notation...", so I wrote everything in binary.
However, upon closer inspection, there was a way to write it in decimal!
In VHDL, the 4-bit 9 in binary is written as "1001",
Just write this as 9! No need to enclose it in double quotes ("")!
However, this is only for the conditional judgment in the if statement (see below).
If you use it when assigning a value, it will be recognized as an integer type and an error will occur, so be careful.
These are the points I stumbled upon when I was making a watch in training.
I learned a little bit about Verilog HDL and VHDL in June's training, but when I started from scratch, there were many things I misunderstood and forgot.
Please use it as a reference.