The key to avoiding overvoltage stress in LVMOS is to use a JFET device structure with Cds=0 to avoid capacitive voltage divider action. In addition, LVMOS is designed with clamping PN junction diodes in each trench MOSFET cell, allowing the device to withstand large and repeated avalanche events indefinitely. This is evidenced by both avalanche mode burn-in and exposure to 1 million cycles of avalanche events without parametric shift.