Microchip FPGA: Is it okay to add user timing constraints to the SDC file automatically generated by Derive Constraints?
We recommend separating the SDC file automatically generated by Derive Constraints from your user timing constraints into separate files.
Bad example: Adding arbitrary timing constraints to the automatically generated <project name>_derived_constraints.sdc file.
Changed the design and IP settings.
Derive Constraints were reapplied to match the revised design.
Any entries you added to <project name>_derived_constraints.sdc will be lost.
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