Microchip FPGA: Is there a way to reduce simulation time when using PolarFire DDR IP?

Narrow down by specifying conditions

There are currently 4341 results.

Microchip FPGA: Are there any ways to reduce simulation time when using PolarFire DDR IP?

IP Libero SoC PolarFire

If you open the Misc. tab in the DDR IP settings screen, you will find the Simulation Options settings.
If you have selected FULL (training and settling time),
One possible solution is to change the settings to skip part of the simulation.

FPGA related materials summary page

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search