Microchip FPGA: When performing synthesis, is it possible to set it so that unnecessary wiring and signals are not deleted by optimization?

Narrow down by specifying conditions

There are currently 4342 results.

Microchip FPGA: When running synthesis, is it possible to set it so that unnecessary wiring and signals are not eliminated by optimization?

Libero SoCs

You can add /* synthesis syn_keep=1 */.
Example: wire sw /* synthesis syn_keep=1 */;

For details, please refer to the section "Using syn_keep for Preservation or Replication" in the Synopsys FPGA Synthesis Synplify Pro ME <version> User Guide.
If you open the User Guides tab in Documentation, you will find the Synopsys FPGA Synthesis Synplify Pro ME <version> User Guide.
https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/synthesis-and-simulation/synplify-pro-me#Documentation

FPGA related materials summary page

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search