<When generating from Libero SoC>
Open the Design Flow tab on the left side of Libero SoC and scroll down.
You can generate an IBIS model from Export IBIS Model in Handoff Design for Production.

<When using DDR>
Please also see the following article: "How to generate the Bi-Directional IBIS simulation models for DQ pins of the DDR controller of PolarFire FPGA."
https://microchip.my.site.com/s/article/How-to-generate-the-Bi-Directional-IBIS-simulation-models-for-DQ-pins-of-the-DDR-controller-of-PolarFire-FPGA

<When downloading from the web>
On the web, the IBIS models can be found on the PolarFire page under Documentation > Data Sheet tab > IBIS Models.
https://www.microchip.com/en-us/products/fpgas-and-plds/fpgas/polarfire-fpgas/polarfire-mid-range-fpgas#Documentation