Microchip FPGA: In the Design Hierarchy of Libero SoC, there is an HDL with "elab0:" at the beginning. What does this mean?

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Microchip FPGA: In the Design Hierarchy of Libero SoC, there is an HDL that starts with "elab0:". What does this mean?

Libero SoCs

For modules that contain parameters, they are displayed as elab0: (for example, parameter WIDTH = 16).

For details, please refer to the "Design Hierarchy in the Design Explorer" section of the "Libero SoC Design Suite v<version> Design Flow User Guide for All FPGA Families."
The documentation can be found under the Documentation > User Guides tab.
Quote: "The parameterized instantiated module will be shown aselab<num>:<modulename>."
https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions#Documentation

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