Microchip FPGA: Is it possible to perform a mixed simulation of VHDL and Verilog?

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Microchip FPGA: Is it possible to simulate a mixture of VHDL and Verilog?

Libero SoCs

This is possible for Libero SoC v11.8 and later. For details, please refer to the Microchip website.

Quote "1. Versions 11.8 and later of Libero SoC Design Suite support mixed-language simulation. Versions 11.7 and earlier of Libero SoC Design Suite support single-language simulation only."
https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/licensing

https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/synthesis-and-simulation/modelsim

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