Microchip FPGA: Understanding TXPLL placement constraint rules. Each Lane_Quad of XCVR has one TXPLL_SSC and two TXPLLs, and if you want to route all 4 Lanes, you must use TX_PLL_SSC. Furthermore, the TXPLL placed above each Lane_Quad can be wired to the top 2 lanes, and the TXPLL placed below can be wired to the bottom 2 lanes. Please give me accurate information about this constraint.

Narrow down by specifying conditions

There are currently 4341 results.

Microchip FPGA: About placement constraint rules for TXPLL. Each Lane_Quad of XCVR has 1 TXPLL_SSC and 2 TXPLL, if you want to route all 4 lanes, you need to use TX_PLL_SSC. In addition, the TXPLL placed on the upper side of each Lane_Quad can be wired to the upper two lanes, and the TXPLL placed on the lower side can be wired to the lower two lanes. Could you please give me the exact information about this constraint?

Libero SoC PolarFire Clock/CCC Transceiver

Please refer to the following document for details.
UG0677 : PolarFire FPGA Transceiver User Guide
https://www.microsemi.com/document-portal/doc_download/136531-ug0677-polarfire-fpga-transceiver-user-guide
Due to the limitation of TX_Bit_CLK described in the figure of 3.5.3 Transmit Lane Alignment,
・The upper two lanes are only TXPLL1
・Lower two lanes are TXPLL0 only
・TXPLL_SSC has 4 lanes
can be driven.

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search