If I want to use a "global clock buffer", it is instantiated in the RTL description for other companies' FPGAs, but is there a specific way to specify it for Diamond?
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Lattice's tools automatically assign the clocks with the highest fanout to the "Primary Clock Network", which corresponds to the global clock net. No need to specify a clock buffer. After placement and routing, the primary clock net can be checked in the "Clock Report" section of the report displayed by selecting "Place & Route" in the "Process Report" section.
If the fanout is too small to automatically assign to the primary clock net and you want to force assignment, please refer to the following procedure.
First, after executing up to the mapping process, launch SSV (Spreadsheet View) and select the "Clock Resource" tab. Specify "Primary" in the "Selection" cell for the listed signal (which the tool recognizes as a clock) and save. Then run through the place and route process and check the report. The information set by SSV is written to the constraint file xxx.lpf. Editing lpf with a text editor is equivalent.
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