Category: Configuration/Programming
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device:-

First, Lattice's terminology distinguishes "configuration" from writing to configuration SRAM, and "programming" from writing to on-chip non-volatile memory such as flash memory (CFM) or NVCM.
When configuring an FPGA from an external CPU, regardless of whether the device has non-volatile memory or not, use a bitstream (*.bit) file generated by the "Export Files" process of tool Diamond/Radiant. JEDEC (*.jed) files are typically used to program the non-volatile memory onboard the FPGA from an external CPU (bitfiles *.bit can also be used).
In Diamond, under the Export Files process in the Process window, check the subprocess "Bitstream File" and/or "JEDEC File" (if applicable) and run. Radiant automatically generates *.bit when you run the same process.
The generated *.bit / *.jed files are output under each implementation name folder in the project folder. The implementation name is "impl1" for Diamond and "impl_1" for Radiant unless the user specifies it when generating the project, so the default name is "project name/impl1" or "project name/impl_1".
In addition, in the MachXO2 / MachXO3 series, it is necessary to generate and instantiate an "EFB (Embedded Functional Block)" macro with the relevant interface enabled in the implementation circuit.