Category:-
Tool: Diamond
device:-

The basis of the fitting is to give the clock frequency constraint. The tool will automatically constrain at 200MHz if you are unconstrained for the clock used. It is usually much lower than this, so the unconstrained case can result in a large circuit consuming more LUT/FF resources than necessary. Add the setting to "Frequency" in the "Timing Preference" tab of Spreadsheet View (SSV), or specify it in text format in the constraint file LPF.

Diamond has a "strategy" that manages design constraints collectively, but the default is "Strategy1", which emphasizes timing. To reduce the circuit size, double-click the active strategy, and in the "Synthesize Design" section of the popup window, set the "Area" option to "True" for "Synplify Pro" and "Optimization Goal" for "LSE". to "Area".

After that, check the MAP report and "Hierarchy" tab to see if there is any deviation from the intended number of resource usage after logic synthesis for each submodule. If it is reasonably higher than the expected number, review the RTL.

The next strategy is to check if it is the FF or LUT that is missing in the MAP report. If your usage is heavily unbalanced, the following settings may help:

[1] Double-click the active strategy, select "MAP Design" in the popup window, and change the option item "Timing Driven Mapping" or/and "Timing Driven Packing" from "False" to "True".
　
[2] Or change the default "0" of "Pack Logic Block Util" in the same "MAP Design" option item.

If the effect above is not sufficient and multiple clocks are used, it may be effective to give each clock frequency constraint to the logic synthesis tool. For Synplify Pro, specify using the sdc/fdc file. For details, please contact our FAE.