Categories:-
tool:-
Device: MachXO2, MachXO3

For Lattice FPGAs and CPLDs in general, it is generally recommended that the input waveform rise time (Tr) and fall time (Tf) be within 50ns. However, if the transition time is longer than recommended, we recommend setting the I/O buffer hysteresis to ENABLE and checking the waveform on the actual device.

See also TN1112 (Input Hysteresis in Lattice CPLD and FPGA Devices) for additional information.