Category: Timing Constraint/Analysis
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FPGA is a device that can freely rewrite any design, but it is realized by changing the wiring between FF and LUT.

Therefore, input port timing should be given as a design constraint to the tool first, based on external requirements. The tool performs place-and-route operations to meet the timing and reports the results. If the constraint requirements cannot be met, it may be necessary to review the circuit to be implemented, or in some cases floorplanning (forcibly specifying the LUT/FF positions) may be required.

Design constraints are given in the GUI of "Spreadsheet View" for Diamond and "Timing Constraint Editor" for Radiant. For details, refer to each tool manual.