I generated multiple ports with the same frequency clock from one PLL and performed Dynamic Reconfiguration to change them to different frequencies, but I was not able to obtain the expected frequencies. What could be the cause?

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I generated multiple ports of clocks with the same frequency from one PLL and changed them to different frequencies by performing Dynamic Reconfiguration, but I could not get the expected frequencies. What is the cause?

Clock/PLL Quartus Prime

Category: Device

A possible cause is that the PLL output counters for each output port have been merged into one due to the same frequency setting.
As a countermeasure, settings must be made to prevent the merging of the PLL output counter.

For details, please refer to the following Knowledge Database (KDB).
https://www.altera.com/support/support-resources/knowledge-base/solutions/rd03062013_146.html

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