If I instantiate a Verilog-HDL instance without declaring a port, how will the undeclared port be handled?

Narrow down by specifying conditions

There are currently 4332 hits.

How are undeclared ports handled when a port is instantiated without declaring it in the Verilog-HDL instance declaration?

Category: Tools
Tools: Quartus® II

Output pins are handled as Open.
Input pins are grounded (fixed to 0) if there is no initial value in the lower layer.

*This is the result of checking with Quartus II v13.1.

Experienced FAE
Free consultation is available.

From specific product specifications to parts selection, the Company FAE will answer your technical concerns free of charge. Please feel free to contact us.

Inquiry form

Site Search