Is there a delay constraint for the misalignment between mem_ck and mem_dqs in the external memory interface?

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Is there a delay constraint on the mem_ck and mem_dqs lag of the external memory interface?

Timing constraints/analysis

Tools: Quartus® II
Categories: External Memory Interfaces, Timing Constraint/Analysis

There is no wiring delay constraint on the difference between mem_ck and mem_dqs of the External Memory Interface (EMIF).
The clock and DQS lag is memory device dependent.

In the TimeQuest Timing Analyzer,

Report DDR ⇒ Before Extra Common Clock Pessimism Removal ⇒ DQS vs CK

It is an indicator that there are no timing violations in

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