Device: Cyclone® V
Category: IP (PCI-Express®)

The polarity of the differential signal is adjusted during linking.
Hard IP for PCI Express has the following signals in the PIPE interface,

rxpolarity<n>_ext / pipe_ext_rxpolarity<n>_ex

You can check if the PHY is inverted in 8b10b with the state of the signal.

Regarding the lane order, there are placement restrictions as follows,

For ×1, Ch0
For ×4, Ch0, 1, 2, 3
For ×8, Ch0, 1, 2, 3, 4, 5, 6, 7

must be placed in order.

Also, for the lanes supported by the IP core,

x1, x2, x4 if the IP core is x4
x1, x2, x4, x8 if the IP core is x8

is supported.

For more information, please refer to the User Guide below.
https://www.altera.com/en_US/pdfs/literature/ug/ug_c5_pcie_avmm.pdf
* Search for "Lane Initialization and Reversal".


Created: October 2014