Using Qsys' Avalon-MM Slave Translator component, you modified the Avalon-MM interface to your specifications and built the design outside of the Qsys system. Qsys' HDL Generate was successful, but an error occurred when compiling with Quartus II. Please tell me how to avoid the error.

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Using Qsys' Avalon-MM Slave Translator component, we have constructed a design that pulls the Avalom-MM interface to arbitrary specifications and pulls it outside of the Qsys system. Qsys HDL Generate is successful, but I get an error when compiling in Quartus II. Please let me know how to avoid the error.

Platform designer IP

Category: Quartus® Prime / Quartus® II (Qsys)
Tools: Quartus® Prime / Quartus® II (Qsys)
device:-

Translator IP cannot be manually added to the Qsys system.

Please refer to the following knowledge database for information.
https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/embedded/2017/can-i-instantiate-avalon-translator-ip-in- a-qsys-system--.html

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