In UniPHY, when using the Hard Memory Controller (HMC), I think that the user circuit side can use a clock other than the clock output from the HMC because of the Multi-Port Front End (MPFE), but is that correct? Or?

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In UniPHY, when Hard Memory Controller (HMC) is used, I think that clocks other than those output from HMC can be used on the user circuit side because of Multi-Port Front End (MPFE). Is that correct? Huh?

Clock/PLL

Tools: Quartus® II
Device: Arria® V
IP: External Memory Controller

Clocks other than those output from the HMC can be used.
The EMIF example design also uses a clock generated by a separate PLL from the HMC.

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