It uses the HPS built-in DMAC of Cyclone V SoC. When I execute a DMA transfer with the transfer completion event enabled, a DONE interrupt occurs before the transfer is completed. Is there a solution?

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It utilizes the HPS built-in DMAC in the Cyclone V SoC. When I enable the transfer completion event of the DMA transfer and execute it, the DONE interrupt occurs before the transfer is completed. Is there a workaround?

SoC FPGAs

Device: Cyclone V
Category: SoC

When programming the microcode for the DMAC, take a workaround by executing a memory barrier instruction for writing (DMAWMB) before issuing a completion event (DMASEV).

The ARM documentation also describes the same workaround.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424d/DDI0424D_dma330_r1p2_trm.pdf * See "Using events and interrupts".

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If you use the DMASEV instruction to notify a microprocessor when the DMAC completes a DMALD or DMAST instruction then ARM recommends that you insert a memory barrier instruction before the DMASEV.
Otherwise the DMAC might signal an interrupt before the AXI transfers complete.
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