Regarding the signal connection of the memory controller (UniPHY) in Stratix V devices, I have two CLK outputs and Fly-by is set to On. Are there any precautions I should take?

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Regarding the signal connection of the memory controller (UniPHY) in the Stratix V device, there are two CLK outputs and Fly-by is set to On. Are there any precautions?

Category: External memory interface
tool:-
Device: Stratix® V

For Fly-by wiring, use Fly-by wiring for both addresses, commands, and clocks.

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